Power hungry buffers and/or large decoupling capacitors have long been the solution to providing accurate reference voltages in pipelined Analog-to-Digital Converters (ADCs). Zero-crossing based pipelined ADCs offer a low power alternative to traditional op-amp based solutions, but their reference buffer design is exacerbated since the reference voltage has only a fraction of the hold phase (known as the pre-charge phase) to settle to the desired accuracy.
Accordingly, new systems and methods for providing a pipelined Analog-to-Digital Converter (ADC) are desirable.